1. Field of the Invention
The present invention pertains integrated circuit fabrication and, in preferred embodiments, to a bottom anti-reflective coating and hard mask for gate patterning and a method for forming the same.
2. Related Art
The escalating requirements for high density and performance associated with ultra large scale integration require responsive changes in conductive patterns, which is considered one of the most demanding aspects of ultra large scale integration technology. High density wiring demands require increasingly denser arrays with minimal spacing between conductive lines. This imposes correspondingly high demands on photolithographic techniques.
Photolithographic techniques form patterns in a photoresist layer using a projected light pattern. However, when a highly reflective substrate such as metal or polysilicon underlies the photoresist layer, reflected light may degrade pattern resolution through several mechanisms. These include off-normal incident light that is reflected into that is intended to be masked, incident light reflected off device features that exposes “notches” in the photoresist, and thin film interference effects leading to linewidth variations when photoresist thickness changes are caused by irregular wafer topography.
These problems are addressed in conventional photolithographic techniques by using an anti-reflective coating (ARC), also characterized as an anti-reflective layer (ARL). This layer is typically positioned between a substrate and a photoresist material. Conventional ARCs are designed, by appropriate adjustment of variables such as composition, deposition conditions and reaction conditions, to provide optical parameters that suppress multiple interference effects caused by the interference of light rays propagating in the same direction due to multiple reflections in the photoresist film. The effective use of an ARC enables patterning and alignment without disturbance caused by such multiple interference, thereby improving line width accuracy and alignment.
It has been found that some line width variations are due to the inability of the ARC to sufficiently reduce reflective layer reflectivity. These reflectivity problems have been addressed by the use of bottom anti-reflective coatings (BARCs) underneath the resists.
In some applications, the BARC serves two functions during semiconductor memory manufacturing: (1) as a hard mask during self-aligned etch (SAE) and during self-aligned-source etch; and (2) as a bottom anti-reflective layer for photolithography at second gate masking.
Silicon oxynitride (SiON) by itself has been used as a BARC material. However, the thickness of SiON required for good hardmask performance is too thick to minimize reflectivity. For example, a typical thickness of a SiON BARC may be 100 nm. This thickness may produce non-uniform line width through lensing effects resulting from variations in the topography of reflective layers under the BARC that are not completely phase cancelled by the BARC. Consequently, a second anti-reflective layer has been used in combination with a SiON layer to improve the performance of the BARC as both a hard mask and a bottom anti-reflective layer for photolithography.
FIG. 1 shows a double layer type BARC using an amorphjous carbon layer. Semiconductor device 100 has a substrate 102. A polysilicon layer 104 with a high reflectivity is formed on substrate 102. The polysilicon layer 104 is to be etched using a BARC as a hard mask. The BARC comprises an amorphous carbon layer 106 and a SiON layer 108. The amorphous carbon layer 106 is formed on top of the polysilicon layer 104. The SiON layer 108 is formed on top of the amorphous carbon layer 106. A photoresist pattern 110 is formed on top of the SiON layer 108 and defines, for example, a line pattern or gate pattern.
A double layer type BARC of the type shown in FIG. 1 has the advantages of allowing the thickness of the anti-reflective layer to be appropriately adjusted to lower the reflectivity and, in addition, allowing the double layer type anti-reflective layer to function as a hard mask for use in an etching process.
However, there are also accompanying disadvantages of the double layer type anti-reflective layer structure shown in FIG. 1. One is that thin nitride layers such as SiON layer 108 are prone to pinhole defects that may affect the reliability of the semiconductor device. One common cause of pinhole defects in a SiON layer is outgassing during the chemical vapor deposition (CVD) process used to form the SiON layer. This outgassing creates localized non-uniformity of the plasma used in the CVD process which results in pinholes in the SiON layer. These pinholes allow nitrogen dopant, which is typically provided in the amorphous carbon to improve the etch selectivity of the amorphous carbon relative to polysilicon, to pass through the SiON layer and contaminate the photoresist. This may prevent the photoresist from being removed during the development process and may result in defects in the pattern subsequently formed in the polysilicon layer or other lithography defects.
Another disadvantage of the semiconductor device 100 shown in FIG. 1 is that there exists a large compressive stress in the amorphous carbon layer 106 that results from large differences in coefficients of thermal expansion (CTE) between the amorphous carbon layer 106, which has a CTE of 3.7 ppm/degree C., and the polysilicon layer 104, which has a CTE of 2.9 ppm/degree C. Because the polysilicon layer 104 contracts to a different degree than the amorphous carbon layer 106 during processing, the amorphous carbon layer 106 is subjected to compressive stress. This stress may cause the patterned amorphous carbon to delaminate from the underlying polysilicon layer and take on a deformed pattern. When the patterned amorphous carbon is subsequently used as a hard mask to pattern the polysilicon layer 104, the deformed pattern is transferred to the polysilicon layer 104.
Yet another disadvantage of the semiconductor device 100 shown in FIG. 1 results from the radiation absorption properties of the amorphous carbon layer 106. One reason for using the amorphous carbon layer 106 in the BARC to absorb ultra-violet (UV) radiation and deep ultra-violet (DUV) radiation. However, amorphous carbon also absorbs radiation in the visible range. This absorption can obscure alignment marks formed on underlying layers that are used to align the various masks formed on the wafer during device fabrication.
These above-described problems make it difficult to control the critical dimensions (CDs) of device features such as transistor gate width, and the alignment of circuit patterns on the wafer. Thus, the semiconductor device may be rejected during a final inspection step due to a deformed pattern on the polysilicon layer or to registration errors.